1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a desired circuit formed by combining and laying out a plurality of standard cells each having transistors and gate electrodes and connecting the cells together.
2. Description of the Related Art
In a common standard cell, at least one of the sizes thereof in the directions orthogonal to each other (so-called vertical and horizontal directions) is standardized to a few types or, for example, to three types. The so-called vertical size is referred to as the height of the standard cell. This height is standardized to three types or so. Here, in order to avoid confusion between this cell size (height) and its structural height perpendicular to the semiconductor substrate, the cell size will not be called the “height.” Instead, this size will be referred to as the “standard cell length” for the sake of convenience.
Even when a few standard lengths of the standard cell may be used in an LSI (Large Scale Integration) as a whole, the same standard length is used when viewed locally as in the same circuit block to ensure efficient layout of cells.
Therefore, various types of standard cells with the same standard cell length are made available and registered in a library. In general, standard cell patterns such as internal wiring patterns are limited in layout space along the standard cell length.
In contrast, the standard cell size in the direction orthogonal to the common cell length (so-called horizontal direction) is available in a variety of lengths according to the scale of the gate circuit. The cell size in the direction orthogonal to the common cell length will be hereinafter referred to as the “arbitrary cell length” for the sake of convenience.
The inverter is normally the most basic building block of logic circuits achieved by the standard cell system. The inverter is formed by connecting NMOS and PMOS transistors in series between VDD and VSS lines so that the gates are shared. In the most basic standard cell used for logic circuits, the distance between the center of the VDD line and that of the VSS line is the standard cell length, and the direction along the VDD and VSS lines is the arbitrary cell length direction when the VDD and VSS lines are arranged alternately and parallel to each other. This most basic standard cell is designed by increasing or reducing the size of the arbitrary cell length as appropriate according to the scale of the standard cell circuit. Such a basic standard cell has a standard cell length of a CMOS pair that is appropriate to the sum of the lengths of NMOS and PMOS gates. Such a standard cell has a height appropriate to that of a single CMOS pair. Therefore, this cell will be hereinafter referred to as a “single height cell.”
The layout of standard cells each having a standard cell length of a CMOS pair is described, for example, in Japanese Patent Laid-Open No. Hei 10-173055.